1. Field of the Invention
The present invention relates to a memory, and more particularly, to a dynamic random access memory (DRAM) having different row to row delay times (tRRD time, hereinafter) and an operation method thereof.
2. Description of Related Art
A conventional semiconductor memory device usually includes a plurality of memory banks. Herein, each memory bank has the same storage space (i.e. having the same number of memory cells) and the same storage capacity. Particularly, the widely used dynamic random access memory (abbreviated as DRAM) is a standard memory structure that usually includes a plurality of memory banks having the same capacity. FIG. 1 is a schematic view illustrating a conventional DRAM structure. A memory 100 includes a memory unit 110 and a driving power 120. Herein, the memory unit 110 includes memory banks 101˜108. When the system selects a row in the memory 100, the driving power 120 provides the voltage used for driving the corresponding circuit.
When the memory 100 receives an active signal, an address buffer receives an address inputted by the system and a row address is generated by a row address generator. According to the row address, the memory 100 reads data from the corresponding memory banks 101˜108. Since the operating frequency of DRAM is very fast, the driving capacity of a single driving power 120 is unable to instantaneously provide the current required for operating the next row. Therefore, there is a delay between successive active signals outputted by the system to allow time for the driving power 120 to restore its driving capacity. This delay is known as the tRRD time in the specification for DRAM. Conventionally, the tRRD time is fixed regardless of whether the operation takes place in the same memory bank (any of the memory banks 101˜108) or in different memory banks 101˜108 such as switching from the memory bank 101 to the memory bank 102. As a result, when the tRRD time is greater than the tCCD time (CAS to CAS delay), the memory 100 is unable to read data consecutively, resulting in bubbles.
FIG. 2 is a schematic waveform diagram illustrating the clocks generated by a conventional art. Please refer to FIG. 1 for the following description. Active signals ACT1 and ACT2 respectively correspond to memory banks 101 and 102. Further, the time interval between receiving active signals ACT1 and ACT2 is tRRD time (i.e. 4 clock cycles in FIG. 2). Take the memory bank 101 as an example. The time interval between receiving the active signal ACT1 and a corresponding read command Read 1 is known as tRCD time (RAS to CAS delay; i.e. 7 clock cycles in FIG. 2). The time interval between receiving the read command Read 1 and outputting the data read to the bus is known as CL (i.e. 7 clock cycles). The same reading procedure applies for reading the memory bank 102. Hence, a detailed description thereof is omitted.
Since there are 4 clock cycles between the active signals ACT1 and ACT2, which is the length of a tRRD time, the time interval between outputting the read commands Read1 and Read2 is also 4 clock cycles. Similarly, regardless of whether the memory 110 reads data from the same memory bank (any of the memory banks 101˜108) or from different memory banks 101˜108, data bubbles are generated because the tRRD time is greater than the tCCD time, lowering the reading efficiency and wasting the system resources.